Voltage regulators based on an N-channel MOS (NMOS) technology are suitable for the control or regulation of severely noisy power supplies. It is disadvantageous, however, that NMOS voltage regulators require a charge pump in order to be able to sufficiently increase the voltage at the gate of the NMOS transistor. In portable applications, in particular, it is disadvantageous, however, that the charge pump has a considerable current consumption during operation.
FIG. 1 shows an in-house conventional circuit arrangement in which the current consumption of the charge pump can be reduced. For this purpose, the charge pump is switched off if the voltage at the gate of the NMOS transistor has assumed the correct value. The circuit arrangement for voltage regulation in FIG. 1 is based in principle on a binary regulation. The circuit arrangement has a first differential amplifier AMP1 and a second differential amplifier AMP2 with two inputs in each case. The noninverting input of the first differential amplifier AMP1 and also the inverting input of the second differential amplifier AMP2 are connected to a reference potential VREF. Via a voltage divider comprising three resistors R1, R2 and R3, the inverting input of the first differential amplifier AMP1 is connected to the potential UP, which is also referred to as first divider voltage, and the noninverting input of the second differential amplifier AMP2 is connected to the potential DN, which is also referred to as second divider voltage. The voltage divider is located between the voltage VDD to be regulated and a reference potential GND. The potential UP can be tapped off between the first resistor R1 and the second resistor R2. The potential DN can be tapped off between the second resistor R2 and the third resistor R3. The output EN of the first differential amplifier AMP1 leads to the input of an oscillator OSZ. The oscillator OSZ with constant frequency generates, if the voltage VDDEXT is present at its input EN, a signal with constant frequency. However, if no voltage is present at its input EN, the oscillator OSZ does not generate a signal at its output either. The output of the oscillator OSZ is in turn connected to the charge pump LP, which generates a voltage depending on the frequency generated by the oscillator OSZ, said voltage being present at the charge pump output 4.1. The output of the second differential amplifier AMP2 leads to the control input of a second NMOS transistor NMOS2. The output of the charge pump LP is connected to the control output of the NMOS transistor NMOS2, a capacitor CAP and the control input of the NMOS transistor NMOS1. The external supply voltage VDDEXT present at the input VDDEXT of the circuit is passed, on the one hand, to the drain terminal of the first NMOS transistor NMOS1 and, on the other hand, to the supply terminal 1.2 of the first differential amplifier AMP1, the control terminal 3.1 of the oscillator OSZ with constant frequency and also to the supply terminal 2.1 of the second differential amplifier AMP2.
The principle underlying the circuit arrangement for voltage regulation as is shown in FIG. 1 consists in using the capacitor CAP as a storage element and, moreover, in switching on the charge pump LP and also the NMNOS transistor NMOS2 only if the voltage at the gate of the NMOS transistor NMOS1 is to be increased or reduced. For the time for which the charge pump LP is switched off, the voltage is stored in the capacitor CAP. The two differential amplifiers AMP1 and AMP2 operate as comparators. A voltage window may be generated with the aid of the reference voltage VREF and the two comparators AMP1 and AMP2. If the supply voltage or operating voltage VDD is too low, that is to say lies outside the voltage window, the charge pump LP is activated. If the supply voltage VDD is too high, the gate of the first NMOS transistor NMOS1 is discharged via the second NMOS transistor NMOS2. As long as the supply voltage VDD lies within the voltage window, neither the charge pump LP nor the second NMOS transistor NMOS2 is activated. The current consumption is thus reduced. Apart from the two differential amplifiers AMP1 and AMP2, neither the oscillator OSZ nor the charge pump LP nor the second NMOS transistor NMOS2 then consume current.
In detail, the circuit illustrated in FIG. 1 functions as follows. If the supply voltage VDD has the nominal value, the reference voltage VREF lies between the potentials UP and DN generated by the voltage divider. The consequence of this is that the voltage at the output EN of the first differential amplifier AMP1 and the voltage at the output PULLDN of the second differential amplifier AMP2 are at the value 0. This in turn has the consequence that the charge pump LP is deactivated and the second NMOS transistor NMOS2 is switched off. The voltage at the node NGATE and thus at the gate of the NMOS transistor NMOS1 is therefore influenced neither by the charge pump LP nor by the NMOS transistor NMOS2. The voltage at the node NGATE is prevented from drifting with the aid of the capacitor CAP.
If the supply voltage VDD assumes an excessively high value, the potential DN rises above the reference voltage VREF. This has the effect that, with the aid of the second differential amplifier AMP2, the voltage at the output PULLDN of the second differential amplifier AMP2 rises from the value 0 to the value of the external supply voltage VDDEXT. The node NGATE and the gate of the NMOS transistor NMOS1 are thus pulled to the reference potential GND via the second NMOS transistor NMOS2. The consequence of this is that the current that flows from the input VDDEXT of the circuit to the output VDD of the circuit decreases. The supply voltage VDD thus decreases until the reference voltage VREF again lies between the two potentials UP and DN.
If the supply voltage VDD decreases to an excessively great extent, the potential UP falls below the value of the reference voltage VREF. The voltage at the output EN of the first differential amplifier AMP1 then changes from the value 0 to the value of the external supply voltage VDDEXT and the oscillator OSZ for generating a constant frequency is activated. The oscillator OSZ generates a signal CLK with a constant frequency, which has the effect that the charge pump LP increases the voltage at the node NGATE. The current that flows between the input VDDEXT of the circuit and the output VDD of the circuit thus increases, which has the effect that the supply voltage VDD rises until the reference voltage VREF again lies between the two potentials UP and DN.
A circuit of this type has the disadvantage, however, that it is designed as a digital system. The circuit is therefore unable to adapt itself to the degree of deviation of the supply voltage VDD. Irrespective of whether the supply voltage VDD is far from its nominal value or close to the latter, the same voltage at the node NGATE is always generated with the aid of the charge pump LP and the second NMOS transistor NMOS2. Therefore, a compromise is required between the regulating speed of the system and the ripple of the supply voltage VDD. If the charge pump LP and the second NMOS transistor NMOS2 are too strong, although the system becomes fast, that is to say the system can then be switched on rapidly and a change in the supply voltage VDD brought about by a change in the load is compensated for rapidly, at the same time the supply voltage VDD has large voltage steps when the charge pump LP, the oscillator OSZ and the second NMOS transistor NMOS2 are switched on and off.